Open-source · Hardware
Complicated AI hardware design,
brought down to earth.
Hotwright's hardware agent generates data path RTL then tackles the complicated problem of algorithm control logic with cycle-accurate state machines.
Don't let AI control you.
Let Hotwright do the control for you.
Edge AI
Tsetlin Machine and spiking neural net classifiers running entirely on-chip — inference with no external NPU
Robotics
Real-time actuator and sensor-fusion loops with cycle-accurate timing, not a scheduled RTOS task
Industrial
PLC-class motor and motion control sequenced by compiled C — deterministic, one instruction per cycle, no ladder logic
Secure IoT
Post-quantum key exchange compiled straight into the control plane, right next to the sensor
What is it
Hotwright's Hardware Agent is an AI hardware harness that manages tools and the hardware sandbox, generates RTL and state machine microcode, and writes documentation.
Hotwright's hardware agent uses an advanced type of state machine called a "Moore Transducer." A transducer is very much like the control of a CPU without the ALU and register file, except it can be applied to any kind of circuit. One of the examples is a RISC-V processor.
The transducer we use is called "The Hotstate Machine." It has some unique features like it is runtime loadable so you can build hardware that can evolve its own microcode. The Hotstate Machine also has its own interrupt that can be triggered in one clock cycle, perfect for edge applications.
Most hardware accelerators aren't limited by arithmetic — they're limited by
the control logic that sequences it: state machines, handshakes, loop
counters, dispatch tables. That control logic is exactly what's tedious and
error-prone to write by hand in Verilog, and exactly what Hotwright compiles
from ordinary-looking C.
if/while/for/switch, functions, _BitInt(N) bit-precise types — compiled to a microcode program, not a general-purpose CPU, that controls your logic.Built with Hotwright's Agentic Technology
A sample of the accelerators in the repo's example suite — every control plane below is compiled C, not hand-written state machine RTL.
RISC-V
A complete RV32IM core with a PicoRV32-compatible PCPI coprocessor interface — plus a 4-wide superscalar variant with hazard detection and branch redirect, and a dual-lane lockstep SIMD variant. All three control planes are compiled from C.
RISC-V · CFU-LI
Attaches sort and matrix-multiply engines to a Linux-capable VexRiscv CPU over the CFU Lightweight Interface — custom RISC-V instructions dispatched straight from the pipeline, handled by a compiled hotstate dispatcher.
Machine learning
A trained Tsetlin Machine MNIST classifier: clause masks extracted from training and stored in ROM, evaluated by a byte-serial hardware engine sequenced by a compiled clause controller.
Machine learning
The Tsetlin Automaton update rule — including the Fuzzy Pattern TM variant — described in C and compiled to hotstate microcode directly, with no hand-written training RTL at all.
Machine learning
A leaky integrate-and-fire SNN for MNIST digits, now reaching 96.2% accuracy with Poisson-encoded spike trains. A sparse-input variant processes only active pixels per timestep for a ~5.6× speedup, validated bit-exact against a quantized Python reference model.
Evolvable hardware
Hardware GA engines evolve cellular automata and Cartesian Genetic Programming LUT-DAG circuits to learn boolean functions — tournament selection, crossover, and mutation running entirely on-chip.
Language
A hardware ASCII tokenizer feeds a bank of per-bit Tsetlin Machines for next-word prediction — a full text pipeline, from raw bytes to prediction, sequenced by compiled C.
Cryptography
A 71-word hand-assembled microcode program sequences a lattice datapath through a full ML-KEM-512 (FIPS 203) encrypt/decrypt — bit-exact against a Python reference model, recovering plaintext from hardware-produced ciphertext.
And more
The example suite covers 90+ designs, from a five-machine Forth
interpreter wired together with --system to a wavefront
systolic array and a hardware-accelerated web server. Browse
examples/ in the repo.
How it fits together
Hotwright lets AI compile your arithmetic. We compile the sequencer that drives it — a small, generic microcode engine called hotstate. This keeps AI from generating convoluted hardwired control logic, and makes code more readable and debuggable. AI can get lost, but Hotwright gives it guidance and structure.
01
.c or hand-written .hasm microassembly. Control flow, bit-precise types, hardware pragmas.
02
hotc compilerLexer → parser → AST → optional CFG/SSA → CompactMicrocode. Hardware variables classified automatically.
03
.memA synthesizable module, testbench, and microcode/variable memory files — plus a symbol table for the simulator.
04
A tiny microcode sequencer instantiated in your design, wired to your own RTL datapath — dividers, BRAMs, DSPs.
05
Open toolchain synthesis via Yosys + nextpnr — ECP5, GateMate, or Gowin — programmed straight to the board.
The AST path (--microcode-hs) goes straight from
the AST to microcode and is tuned for the hotstate microarchitecture — used
in most examples. The CFG/SSA path (--microcode-ssa)
builds a full control-flow graph with SSA-based constant and copy
propagation, and also accepts LLVM-IR as an alternate frontend.
Compile several C files as independent hotstate machines with
--system; matching output/input names are wired automatically
as internal signals. For one-cycle pulses that can't be dropped even if the
receiver is busy, __send/__recv intrinsics generate
a registered latch instead of a bare wire.
--runtime-load and --profile compile against a
fixed hardware envelope so multiple programs can hot-swap on the same
silicon — dual-bank ping-pong memory means a new microcode program can load
while the old one keeps running.
Under the hood
Routes multi-bit relational comparisons around the variable lookup table instead of into it. On a 10-comparator clause sequencer this cut the truth table from 16,384 rows to 16 — an 11.7% total LUT reduction on a Tang Nano 9K.
The __bram qualifier requests registered block-RAM reads
instead of distributed-LUT lookups; writable dual-port BRAM arrays get
write-first semantics with no manual timing code.
--axi-lite generates a memory-mapped register slave and a
matching C header, with optional IRQ signaling — ready to drop into a
larger SoC.
.hasm files give direct, cycle-level control over the
generated microcode when you need to hand-optimize an inner loop or bypass
the C frontend entirely.
Feed hotc Clang-emitted LLVM-IR instead of C — hardware
variables are discovered from LLVM globals and basic blocks map onto the
same CFG/SSA representation.
A standalone C++ simulator loads the generated memory files and plays them back cycle-by-cycle, with an interactive debugger, breakpoints, watch variables, and VCD/CSV/JSON export.
Where it runs
Every example synthesizes through the open-source FPGA toolchain — no vendor IDE required.
OrangeCrab r0.2 (ECP5-85K) — via Yosys synth_ecp5, nextpnr-ecp5, and DFU programming.
GateMateA1-EVB — via synth_gatemate and nextpnr-himbaechel, SRAM or SPI-flash programming.
Tang Nano 9K and Tang Nano 20K — used for the Tsetlin Machine and Fuzzy Pattern TM training examples.