Open-source · Hardware
You have the right to a great design
Anything you say can and will be used to create your design
You have the right to an Agent
If you cannot find an Agent, one will be assigned to you
Agent Hotwright views your datapath as discrete, stateless execution units driven by runtime loadable microcoded finite state transducers, generating the RTL becomes a much more deterministic and reliable task
Put Agent Hotwright in control!
Edge AI
LLMs, neural nets, neuromorphic spiking neural nets and Tsetlin machines. Both inference and on-chip training can be achieved at the edge without sending user data to the datacenter
Robotics
Real-time actuator and sensor-fusion loops with cycle-accurate timing, not a scheduled RTOS task. Change your hardware using Genetic algorithm accelerators
Industrial
PLC-class motor and motion control sequenced by compiled C — deterministic, one instruction per cycle, no ladder logic
Secure IoT
Post-quantum key exchange compiled straight into the control plane, right next to the sensor
Agent's Credo
Agent Hotwright utilizes a hardware harness to manage tools and designs. The Agent generates data path RTL and control path C. This is turned into data path compute and state machine microcode. The system further streamlines development by automatically writing testbenches, generating documentation, and managing the overall design.
Agent Hotwright uses an advanced type of state machine called a "Moore Transducer." A transducer is very much like the control of a CPU without the ALU and register file, except it can be applied to any kind of circuit.
Separating the control path via Moore transducers simplifies the architectural problem down to pure combinational or local arithmetic blocks. Since an AI agent can treat the datapath as discrete, stateless execution units driven by runtime loadable microcoded finite state transducers, generating the RTL becomes a much more deterministic and reliable task.
The transducer we use is called "The Hotstate Machine." It has some unique features like it is runtime loadable so you can build hardware that can evolve its own microcode. The Hotstate Machine also has its own interrupt that can be triggered in one clock cycle, perfect for edge applications.
Most hardware accelerators aren't limited by arithmetic — they're limited by
the control logic that sequences it: state machines, handshakes, loop
counters, dispatch tables. That control logic is exactly what's tedious and
error-prone to write by hand in Verilog, and exactly what Hotwright compiles
from ordinary-looking C.
if/while/for/switch, functions, _BitInt(N) bit-precise types — compiled to a microcode program, not a general-purpose CPU, that controls your logic.Built with Hotwright's Agentic Technology
A sample of the accelerators in the repo's example suite — every control plane below is compiled C, not hand-written state machine RTL.
RISC-V
A complete RV32IM core with a PicoRV32-compatible PCPI coprocessor interface — plus a 4-wide superscalar variant with hazard detection and branch redirect, and a dual-lane lockstep SIMD variant. All three control planes are compiled from C.
Machine learning
A leaky integrate-and-fire SNN for MNIST digits, now reaching 96.2% accuracy with Poisson-encoded spike trains. A sparse-input variant processes only active pixels per timestep. Validated bit-exact against a quantized Python reference model.
RISC-V · CFU-LI
Attaches sort and matrix-multiply engines to a Linux-capable VexRiscv CPU over the CFU Lightweight Interface — custom RISC-V instructions dispatched straight from the pipeline, handled by a compiled hotstate dispatcher.
Machine learning
A trained Tsetlin Machine MNIST classifier: clause masks extracted from training and stored in ROM, evaluated by a byte-serial hardware engine sequenced by a compiled clause controller.
Machine learning
The Tsetlin Automaton update rule — including the Fuzzy Pattern TM variant — described in C and compiled to hotstate microcode directly, with no hand-written training RTL at all.
Evolvable hardware
Hardware GA engines evolve cellular automata and Cartesian Genetic Programming LUT-DAG circuits to learn boolean functions — tournament selection, crossover, and mutation running entirely on-chip.
Language
A hardware ASCII tokenizer feeds a bank of per-bit Tsetlin Machines for next-word prediction — a full text pipeline, from raw bytes to prediction, sequenced by compiled C.
Cryptography
A 71-word AI assembled microcode program sequences a lattice datapath through a full ML-KEM-512 (FIPS 203) encrypt/decrypt — bit-exact against a Python reference model, recovering plaintext from hardware-produced ciphertext.
And more
The example suite covers 100+ designs, from a five-machine Forth
interpreter wired together with --system to a wavefront
systolic array and a hardware-accelerated web server. Browse
examples/ in the repo.
How it fits together
Hotwright lets AI compile your arithmetic. We compile the sequencer that drives it — a small, generic microcode engine called hotstate. This keeps AI from generating convoluted hardwired control logic, and makes code more readable and debuggable. AI can get lost, but Hotwright gives it guidance and structure.
01
.c or hand-written .hasm microassembly. Control flow, bit-precise types, hardware pragmas.
02
hotc compilerLexer → parser → AST → optional CFG/SSA → CompactMicrocode. Hardware variables classified automatically.
03
.memA synthesizable module, testbench, and microcode/variable memory files — plus a symbol table for the simulator.
04
A tiny microcode sequencer instantiated in your design, wired to your own RTL datapath — dividers, BRAMs, DSPs.
05
Open toolchain synthesis via Yosys + nextpnr — Gowin, ECP5, or Xilinx 7-series — programmed straight to the board.
The AST path (--microcode-hs) goes straight from
the AST to microcode and is tuned for the hotstate microarchitecture — used
in most examples. The CFG/SSA path (--microcode-ssa)
builds a full control-flow graph with SSA-based constant and copy
propagation, and also accepts LLVM-IR as an alternate frontend.
Compile several C files as independent hotstate machines with
--system; matching output/input names are wired automatically
as internal signals. For one-cycle pulses that can't be dropped even if the
receiver is busy, __send/__recv intrinsics generate
a registered latch instead of a bare wire.
--runtime-load and --profile compile against a
fixed hardware envelope so multiple programs can hot-swap on the same
silicon — dual-bank ping-pong memory means a new microcode program can load
while the old one keeps running.
Under the hood
Routes multi-bit relational comparisons around the variable lookup table instead of into it. On a 10-comparator clause sequencer this cut the truth table from 16,384 rows to 16 — an 11.7% total LUT reduction on a Tang Nano 9K.
The __bram qualifier requests registered block-RAM reads
instead of distributed-LUT lookups; writable dual-port BRAM arrays get
write-first semantics with no manual timing code.
--axi-lite generates a memory-mapped register slave and a
matching C header, with optional IRQ signaling — ready to drop into a
larger SoC.
.hasm files give direct, cycle-level control over the
generated microcode when you need to hand-optimize an inner loop or bypass
the C frontend entirely.
Feed hotc Clang-emitted LLVM-IR instead of C — hardware
variables are discovered from LLVM globals and basic blocks map onto the
same CFG/SSA representation.
A standalone C++ simulator loads the generated memory files and plays them back cycle-by-cycle, with an interactive debugger, breakpoints, watch variables, and VCD/CSV/JSON export.
The Screen canvas
Open a Screen tab in Agent Hotwright and it becomes a virtual display that your FPGA fills over its own USB serial port. Click Render: the page sends the board a command, the board sends back pixels, and they are painted as they arrive. No HDMI output and no capture card. The board's USB cable is enough.
01
A short Python script from the Screens panel sets up the tab: its size, its controls, and how to read the reply.
02
The script packs the view into the exact command bytes your design expects, and Studio sends them to the board.
03
Web Serial in Chrome and Edge, with nothing to install. In other browsers, a small bridge script from hotc carries the bytes.
04
A design built in Studio: a UART block wired to your engine. The board computes the frame itself.
05
Studio waits for the reply header, then paints each pixel as it arrives: palette, grey, RGB332, RGB565 or RGB888.
A click on the picture, or one of the script's own buttons, changes the view, and the board renders again at once. The bundled Mandelbrot screen zooms in 2× wherever you click, and steps the engine's PLL clock a megahertz at a time with ▲ and ▼.
A serial link has no flow control of its own. With credit turned on, the board sends only what the page has granted, so a slow USB bridge never drops a pixel. On a Tang Nano 20K at 1.5 Mbaud that runs at the bridge's full ~85 KB/s.
Every Screen tab is its own screen with its own script, picture and connection. Screens on different boards each get their own port. Screens on the same board share one link.
Screen scripts
Studio doesn't need to know what your board computes. A screen script tells it. Screen scripts are plain Python: real CPython running in your browser (Pyodide), standard library only, so your design never leaves your machine.
def setup():
return {
"title": "Test card",
"width": 128, "height": 96,
"controls": [{"key": "invert", "label": "Invert",
"choices": [[0, "no"], [1, "yes"]]}],
"reply": {"header": "TC", "format": "gray8"},
}
def command(view):
# 'T', W (u16), H (u16), invert
w, h = view["width"], view["height"]
return (b"T" + w.to_bytes(2, "little")
+ h.to_bytes(2, "little") + bytes([view["invert"]]))setup() describes the page,
command(view) returns the bytes Render sends, and the optional
click() and button() change the view when you click the picture
or press one of the script's buttons./sandbox/screens, where it appears in the panel
straight away..py file.
Hand it to anyone running the same design, or post it on the forum,
and it works on their board as it does on yours.A typical flow
Every step happens in Agent Hotwright, in your browser.
01
Describe what each block should do. The agent turns it into a written spec.
02
Some blocks need new RTL. Check the AI-generated spec first, then generate.
03
Connect the blocks into a design and pick the I/O pads on your board.
04
Yosys synthesizes the design. nextpnr places and routes it into a bitstream.
05
Download it to the board, then talk to the board from the Screen tabs.
Where it runs
Synthesis, place-and-route and programming all run in your browser on the open-source toolchain: Yosys and nextpnr compiled to WebAssembly. No vendor IDE, no Vivado, nothing to install.
Sipeed Tang Nano 9K and 20K, Tang Primer 25K, Tang Mega 138K and Tang Console 138K. Built with
synth_gowin, nextpnr-himbaechel and Apicula, and loaded over the board's own USB.
OrangeCrab r0.2 (ECP5-85K) and Radiona ULX3S (12F to 85F). Built with synth_ecp5 and
nextpnr-ecp5, then flashed over DFU or loaded into SRAM.
Digilent Arty S7-25 and S7-50, the Digilent Basys 3 and Cmod A7-35T (Artix-7 35T), and the Real Digital Blackboard's
Zynq-7007S fabric. Built with
synth_xilinx and nextpnr-xilinx, with the bitstream assembled in the browser.
Coming next: the Lattice CrossLink-NX evaluation board. Its board profile is in place, and it is waiting on an open-source place-and-route build.
Get Started
Two tools, both running entirely in your browser — no install, no account for the sandbox.
Supported boards: Sipeed Tang Nano and Tang Mega, Digilent Arty S7 and Basys 3, and the ULX3S (Lattice ECP5).
Compiler + toolchain
Explore the Hotstate machine. Start with an example then modify it. We generate a Verilog template, then simulate, synthesize, and place-and-route it — Yosys and nextpnr run as WASM, entirely client-side. Save the results for use in any tool chain that supports SystemVerilog. No sign-up required.
Design tool
Let our agentic technology generate, test and document your design ideas come to life.
We use your AI so you don't pay us for tokens. Watch your board draw its results on the Screen canvas.
We support the open source chain:
Yosys, Verilator, and Nextpnr
Free 14-day trial, no card needed, then $20 per month or $120 per year.